The present invention relates to a semiconductor device and is relates to the semiconductor device which includes, for example, an electrostatic destruction protection circuit which protects elements formed in a semiconductor chip against electrostatic destruction.
In the semiconductor device, the electrostatic destruction protection circuit is incorporated for the purpose of protecting the elements which configure an internal circuit against the electrostatic destruction. One example of the electrostatic destruction protection circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2011-254100.
The semiconductor device described in Japanese Unexamined Patent Application Publication No. 2011-254100 has first and second power source cells which correspond to first and second power source pads which supply first and second power source voltages, an input/output cell which corresponds to a first signal pad, a first power source line which supplies the first power source voltage and a second power source line which supplies the second power source voltage. Then, the input/output cell has a circuit which performs signal inputting and outputting, the electrostatic protection circuit and a first MOS which is arranged between the first power source line and the second power source line. The first power source cell has a time constant circuit which temporarily turns the first MOS on in response to positive static electricity of the first power source pad and a unidirectional element which makes a current directing toward the first power source pad flow. The second power source cell has a time constant circuit which temporarily turns the first MOS on in response to the positive static electricity of the second power source pad and a unidirectional element which makes a current directing toward the second power source pad flow. A gate and a well of the first MOS are coupled to the time constant circuits.